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AbstractWhile the electronics industry continues to strive towards miniaturization, it is important to understand the fundamental issues that are a result of the increased package density. Current standard surface mount devices such as peripheral leaded packages and area array (Ball Grid Array) devices offer robust assembly yields and good long term solder joint reliability. When developing a new device or packaging method, it is critical that these must compare to or perform better than standard devices. Not only should the new device perform well in assembly, they must show acceptable package and solder joint reliability in order to gain acceptance and wide use. In an attempt to achieve the functionality and density of bare die assembly, a series of devices known as Chip Scale Packages (CSP), have been developed by the packaging industry which are very close to the dimensions of the bare silicon die. While CSPs have been used extensively in low I/O areas such as memory applications, use of CSPs in more demanding environments and applications has been adopted less readily. This paper describes some of the fundamental issues associated with CSP package reliability. Specifically, assembly process parameters, material selection and board geometry affect the yields and reliability during attachment of CSPs onto organic motherboards. Factors such as presence of voids, reflow atmosphere, attachment pad metallurgy and assembly parameters such as solder paste or flux, show dramatic differences in accelerated thermal cycle testing. This paper discusses some of the basic assembly and Printed Circuit Board (PCB) parameters that influence the success of CSP assembly and solder joint robustness. CSPs have been assembled using conventional surface mount techniques and the long-term solder joint reliability has been assessed using accelerated thermal cycle testing and various mechanical testing methods. Reliability modeling has been performed using the finite element method to compare predicted fatigue lives with test data from both 0-100C and -40- 125C thermal cycles. CSPs have emerged as an area array packaging alternative for applications requiring low to medium input / output counts on limited Printed Circuit Board (PCB) real estate. Due to their leadless (in general) configuration, larger ball pitch, and compatibility with existing standard surface mount PCB assembly equipment, CSPs avoid a significant segment of the assembly problems encountered in fine pitch peripheral leaded device assembly. However, while the use of CSPs has been steadily increasing, it is not considered significantly widespread beyond memory device applications. The explosive growth in CSP development in recent months has been fueled by the promise of high assembly yields and low package cost. The trend towards minimal package design is apparent with the release of numerous wafer scale packages, which are often Si die with one or more redistribution layers. One significant issue concerning CSP as well as ball grid array (BGA) process development has been in the area of joint quality and inspection. Often area array devices are suspect in the test and burn in stage of production due to the inability to visually inspect the joints. While transmission X-ray inspection can assist in inspection of joint related parameters such as voids, the impact on joint integrity is difficult to measure. This paper addresses some of the PCB factors that influence the reliability of area array devices, in particular CSPs.Do you want to read the rest of this article?
CitationsCitations7ReferencesReferences4Sample t-test statistics are mentioned inTable 2. With decreasing pad diameter, the solder joint reliability was seen to increase (Figure 8). Smaller pads increase standoff and trace routing density [Primavera, 1999]. The pad diameter could be decreased with a corresponding result of increase in standoff and reliability upto a certain limit beyond which placement yield is affected. Article · Jan 2001 · International Journal of Advanced Manufacturing TechnologyArticle · International Journal of Advanced Manufacturing TechnologyABSTRACT: This paper presents a theoretical yield model for area array solder interconnect process. To achieve a successful solder joint, contact between the solder ball and its associated wettable pad area is essential because without contact, the solder ball cannot initiate wetting its associated pad and, finally, is found an open defect. When an area array solder joints are made simultaneously, it may happen that some of the solder joints in a chip cannot make contact with their associated pads because of the variations of design parameters such as solder ball size, pad size and height, substrate warpage, etc. The yield model provides the relationships of the interconnect yield to the statistical variations of the design parameters. A series of experiments were performed with specially designed area array flip-chips and substrates to verify the model, focusing on the effects of the solder ball size variation and the number of solder joints on interconnect yield. The experimental observations agree well with the model prediction.Article · Nov 2005 ABSTRACT: Purpose – To design a flexible integrated robotic assembly and rework (remanufacturing) cell for assembly, selective assembly and rework of advanced surface mount components (SMCs) using the generic methodology developed in this paper. Design/methodology/approach – Manual rework procedures are investigated for all advanced SMCs. General and specific component-related rework considerations are obtained and necessary tooling candidates for automation are determined. This is followed by determination of the specific automated rework procedure and selection of suitable tooling for automated robotic rework and generation and evaluation of design concepts. Findings – The developed methodology, which considers the reflow tool at the centre of the development process, has worked well in designing a flexible integrated robotic assembly and rework cell. Practical implications – This study identified the rework requirements for advanced SMCs, the essential features for rework reflow tools, criteria for comparing reflow tools, and a generic procedure for design and concept selection. Originality/value – It provides valuable knowledge for designers of flexible integrated robotic assembly and rework cells for assembly, selective assembly and rework of advanced SMCs.Article · Jan 2006 ABSTRACT: Increasing product complexity, decreasing component size, and using double-sided boards have made surface mount technology
(SMT) based electronics manufacturing (EM) components more difficult to assemble. This has resulted in the economic troubleshooting
of EM defects being one of the main problems facing all manufacturers. Although the authors have made significant improvements
in the EM process, it has been shown that the implemented changes in the automated lines have not yet produced a high enough
percentage of reliable finished products. The objective of this current development is to make a contribution towards these
EM processes by creating an Internet-based intelligent system of circuit board defect detection so that EM process flaws that
necessitate rework operations can be identified prior to manufacturing runs. With the development of this system, the need
to rework the defective components will be minimized for any assembly line and assembly line process parameters, which cause
some reliability problems (such as solder balls, insufficient solder at joints, burnt joint connections, bridged leads, voids,
skewed leads, and unformed joints) will be troubleshot directly, and the rework will be greatly reduced from the EM assembly
line. This paper reports the current development and its structure.Article · Feb 2006 ABSTRACT: The consumer's interest for smaller, lighter and higher performance electronics products has increased the use of ultra fine pitch packages, such as Flip Chips and Chip Scale Packages, in printed circuit board (PCB) assembly. The assembly processes for these ultra fine pitch packages are extremely complex and each step in the assembly process influences the assembly yield and reliability. Generally speaking, end-of-line SMT defects can be greatly influenced by the stencil printing operation. The importance of the stencil printing process progressively increases as the pitch and the package size decreases. A thorough understanding of basic stencil printing principles would facilitate the design of printers, stencils and pastes, and would ultimately permit the extension of reliable print techniques to the ultra fine print arena. Stencil design and stencil fabrication techniques are critical factors that affect the stencil printing process. This work compares the stencil design elements, such as aperture wall taper and aperture wall finish that play a major role in the print performance of the small apertures. Designed experiments are performed to determine the 'optimum' level of aperture taper and aperture wall finish. The study also compares three major stencil-manufacturing techniques (chemical etching, laser cutting and electroforming) for small aperture printing. From the knowledge gathered, guidelines are being developed for the stencil design and the stencil printing process for small apertures.Article · Jan 2008 · International Journal of Advanced Manufacturing Technology Full-text · Article · Jan 1999 +1 more author...Conference Paper · Sep 2016 Thesis · Oct 2014 Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.This publication is from a journal that may support self archiving.您所在位置： &
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影像诊断报告书写技巧规范（X线、CT、MRI） 第1章 传统X线诊断报告书写技巧?第1节??头颅1、???鼻窦（1）?鼻窦炎 右侧额窦、左侧上颌窦窦腔密度增高，透过度减低，右侧上颌窦黏膜增厚。窦壁骨质结构未见异 常。余未见异常发现。（2）?鼻窦囊肿 右侧上颌窦腔底壁可见边缘光滑的半圆形软组织密度影，右侧上颌窦腔扩大，右侧上颌窦粘膜下 皮质白线连续；余鼻旁窦窦壁粘膜光滑，粘膜下皮质白线清晰。（3）良性肿瘤 右侧筛窦窦壁旁小圆形骨性密度影，内可见骨小梁。其余诸鼻旁窦窦腔透过度良好，窦壁光滑。 余骨质未见异常。双鼻甲肥厚。（4）恶性肿瘤 左侧上颌窦窦腔扩大，其外侧壁轮廓模糊、骨质疏松，窦壁骨质呈溶骨性骨质破坏、消失；左侧 上颌窦内侧骨壁模糊。右侧上颌窦窦腔密度增高，透光度减低，为合并上颌窦炎。2、眼眶（1）肿瘤 右眼眶普遍性扩大，右眼眶内骨质破坏、吸收，右上颌窦深部顶壁－眼眶底壁下陷，右眼眶外侧 壁骨缘不连续，呈溶骨性骨质破坏改变。左眼眶未见异常发现。（2）眼异物 右眼眶内偏外侧可见一圆形异物影，直径约5.0mm，边界光滑锐利，侧位可见异物位于球内，距 角膜缘约15.0mm。局部骨质未见异常。3、耳部（1）中耳乳突炎 右侧乳突气房发育尚可，但透光度减低，密度增高。乳突蜂房骨性间隔厚薄不均。未见骨质破 坏。左侧乳突气化良好，其内未见异常密度影，乳突蜂房骨性间隔厚薄均匀、清晰完整。（2）胆脂瘤 右耳乳突气化不良，透光度减低，右耳上鼓室稍扩大，边缘骨质呈硬化改变，前鼓嵴变尖，听小 骨吸收；鼓窦入口受侵略开大。4、鼻、咽、喉部（1）腺样体肥大 鼻咽顶后壁软组织肿胀，厚约10mm，气道明显受压变窄。（
正在加载中，请稍后...扫描所见肝S7段见一类圆形稍低密度影，边界清楚，CT值...
扫描所见肝S7段见一类圆形稍低密度影，边...
病情描述（发病时间、主要症状、症状变化等）：扫描所见肝S7段见一类圆形稍低密度影，边界清楚，CT值约36Hu，直径约1.5cm。这个是什么情况，是否需要做进一步检查？曾经治疗情况和效果：常规检查发现的。想得到怎样的帮助：请医生帮我做一个初步的判断。
医院出诊医生
擅长：小儿内科
擅长：外科
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因不能面诊，医生的建议仅供参考
职称：医生会员
专长：内科、高血压、胸腔积液、
&&已帮助用户：26688
问题分析：从您提供的病情描述分析：您在做肝脏CT时发现，类圆形稍低密度影，边界清楚，CT值约36Hu，直径约1.5cm，要考虑为：肝内实质性占位，边界清楚则提示：以肝内血管瘤的可能性大。意见建议：注意休息，保证睡眠，加强锻炼以增强体质，避免情绪激动和精神紧张。清淡温软富有营养的饮食，避免辛辣刺激生冷油腻食物和酒精制品，戒烟。您可以去医院做肝脏加强CT，化验甲胎蛋白等肿瘤标记物等，根据检查结果，考虑下一步措施。
职称：主治医师
专长：心肺病、心血管疾病等
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问题分析：你好！从你的CT报告看：根据病灶的形态、大小、CT值，初步考虑血管瘤的可能性大。意见建议：建议你正规医院进一步检查，可以行腹部CT增强或MR检查，可以明确诊断不用担心
问扫描层面肝S8和S7段各见一类圆形低密度影.CT值为30HU和...
职称：副主任医师
专长：脑出血,脑积水,脑瘤
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指导意见：你好，脾大主要是由于其他基础疾病引起的,或是感染引起脾功能亢进引起的脾大.这样的情况主要是考虑有胃病,以及咽炎的可能,或是其他的疾病.建议先到医院消化内科做个胃镜的检查,然后再检查其他.平时注意休息,加强　营养,保持心情舒畅 ,禁辛辣食物,多吃蔬菜,水果等,注意定期复查,祝您早日康复
问肝大小、形态正常，肝实质密度均匀减低，CT值约为36hu...
职称：医生会员
专长：肝胆胃肠、糖尿病、冠心病、高血压等内科疑难病的中西医结合诊治。
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问题分析：肝实质密度均匀减低可能的疾病有肝囊肿，肝内血管瘤,肝内肿瘤和肝内的脓肿等可能。意见建议：建议您行腹部彩超，肝功能，肿瘤标记物甲胎蛋白AFP等进一步检查明确诊断，要注意清淡饮食，避免辛辣刺激食物，戒烟戒酒。
问CT结果扫描层面肝S8段及S7段各见一类圆形低密度影，CT...
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专长：脑出血,脑积水,脑瘤
&&已帮助用户：211416
指导意见：　多数多数先天性肝囊肿是在无意中发现的,而又无症状,所以不需治疗,只要定期复查即可。
问CT值约+36HU，边缘可看见多个短毛刺
职称：医师
专长：内科常见疾病
&&已帮助用户：51493
病情分析：你好，对于你的CT检查结果，考虑存在肺癌的可能，建议最好进行一个穿刺活检
意见建议：
问常规检查发现
职称：医生会员
专长：皮肤
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你好，请问目前有什么不适的感觉,说一下主要的症状,必须检查和症状相结合，需要全面分析，综合考虑．
问做的白带常规检查发现有问题
职称：护士
专长：感冒,肺脓肿,呼吸衰竭,肺炎,肺栓塞,肺水肿
&&已帮助用户：0
根据你的检查结果，诊断是细菌性阴道炎合并霉菌性阴道炎。治疗上建议使用克霉唑栓剂，同时口服甲硝唑，7天一疗程，再复查看看。
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